多时钟系统下跨时钟域同步电路的设计

The design of synchronization circuit for crossing the clock domain in multi clock system

针对当前SOC内部时钟越来越复杂、接口越来越多以及亚稳态、漏信号等常见的各种问题,分析了以往的优化方法的优缺点,然后从电路的角度出发,提出了一种新的SOC跨时钟域同步电路设计的方法。这种方法电路简单,可靠性高,通过仿真实验和实测实验验证,能够在多时钟系统中适应最小输入脉宽、不漏信号、避免误触发和多触发,且很好地解决了亚稳态等问题。

In view of the current problems more complex, more and more SOC internal clock interface and metastability, leakage and other common signal, we analyze the advantages and disadvantages of previous methods of optimization, then, starting from the circuit point of view,we put forward a kind of interface and clock domain signal method SOC new asynchronous. This method has simple circuit and high reliability. It can be adapted to minimum width of input pulse and verified by simulation and experiment. It can not leak signal, avoid false triggering and multiple triggers, and solve the problem of sub steady state.