基于EP3C40的FPGA最小系统设计和实现

Design and Implementation of FPGA Minimum System Based on EP3C40

本文介绍了基于Altera公司Cyclone III系列的EP3C40 FPGA最小系统的设计和验证过程,详细介绍了高速FPGA电路设计、PCB电路板设计和数字系统集成设计等相关设计.FPGA最小系统硬件设计包括时钟、电源、存储器、接口、配置、以及USB Blaster等部分,最小系统的功能验证包括键盘和LCD控制、总控制、DDS模块等。最终测试结果表明,本系统工作正常,DDS时钟频率可以达130MHz.

This paper illustrates the design and verification of a minimum SOPC system based on Altera CYCLONE III FPGA EP3C40, and introduces the design process of high speed FPGA circuit, design of PCB circuit board and digital system integration. The FPGA- based minimum system hardware contains design works of clock, power supply, memory, USB Blaster, peripheral and configuration circuit, then verification works include keyboard, LCD controller, master controller, and DDS module. Finally, the test results suggest that the FPGA minimum system works well under the laboratorial environment and the DDS module could run on up to 130MHz.