VHDL数字系统设计实验教学研究

The Experimental Teaching Research of VHDL Digital System Design

VHDL数字系统设计实验课程已建成立体化教学资源,自主开发了EDA实验平台,建成含课堂视频、实验指导视频、电子教案、网上信息发布、师生互动等的课程网站;还精心设计了实验内容,安排了由浅入深的基本模块电路设计、简单综合设计、接近工程实际的复杂设计3个层次实验;改革实验教学方法,提供全方位的实验教学指导;加强学生实验过程管理,开发并使用了现场电脑打分系统;完善有效的实验考核方案。结果表明:该一系列措施在实验教学体系建设方面取得了较好成绩,使实践课达到了教学直观和知识系统化的目的,学生普遍反映受益匪浅。

The experimental courses of VHDL digital system design have been built with 3-dimensional teaching resources. We have independently developed the EDA experimental platform, built the course Website containing classroom video, experimental guidance video, electronic lesson plans, online information release and teachers-students interaction, etc. We designed carefully the experiment content, arranged the three levels of experiment from the shallower to the deeper ones, i. e., the basic module circuit design, simple comprehensive design and closer to the practical engineering of complex design. We reformed experiment teaching methods, provided a full range of experimental teaching guide. We also strengthened the management of students＇ experimental process,developed and used the on-site computer scoring system and effective experiment appraisal scheme. The results show that the series of measures have achieved good effects in the construc-tion of experimental teaching system, successfully made the practice course to have good effect in both teaching intuition and knowledge systematization, students generally reflect the benefits.