摘要
介绍了BCH码传统查找表算法与改进查找表算法,以(15,5,7)BCH码为例,对比研究了这两种算法对纠三错BCH码的译码性能,并对改进算法进行了FPGA设计。研究结果表明:改进算法的资源消耗更低,译码速度更快;译码器的实现方案简单、资源消耗小、译码迅速,易于实现。
The traditional lookup table decoding algorithm and the improved lookup table decoding algorithm for BCH code are introduced is this paper. The(15,5,7)BCH code is used as an example,the decoding performances of the triple-error-correcting BCH code based on these two algorithms are compared. Based on the improved lookup table decoding algorithm,a FPGA-based(15,5,7)BCH code decoder is designed. The results of the research show that the improved algorithm is characterized by low resources cost and high decoding speed relative to the traditional algorithm. The design scheme of the decoder based on the improved algorithm features has simpler structure,smaller device utilization coast and faster speed,and it is easy for project implementation.
出处
《计算机与数字工程》
2018年第2期247-250,275,共5页
Computer & Digital Engineering
关键词
BCH码
纠三错
查找表
译码
FPGA
BCH code
Triple-error-correcting
lookup table
decoding
FPGA