基于FPGA的全数字锁相环的复频域分析与实现

The analysis and implementation of complex frequency domain in FPGA-based all-digital phase-locked loop

模拟锁相环在高频场合存在稳定性差和抗干扰能力弱的问题,导致其应用受到限制,而全数字锁相环不存在这些问题,因此设计一种全数字锁相环用于高频场合是必要的。通过分析触发器型全数字锁相环的工作原理,建立了复频域数学模型,并以此分析了锁相环的全局稳定性和动态响应,提出了模型中各参数的约束条件。采用Xilinx ISim仿真和FPGA硬件实现的方法设计了一种全数字锁相环,结果表明该锁相环具有锁相范围宽、动态响应快和稳态误差小的特点,具有一定的应用价值。

Line phase-locked loop has poor stability and weak anti-interference ability in the application of high frequency,so its application is limited. While the all-digital phase-locked loop has not these problems,the design of an all-digital PLL for high frequency applications is necessary. The complex frequency domain mathematical model is built through analyzing the working principle of flip-flop all-digital phase-locked loop. Meanwhile,the global stability,dynamic response of the phase-locked loop are analyzed by this model and the parameter constraints relation is proposed. A kind of all-digital phase-locked loop is designed by Xilinx ISim simulation and FPGA hardware implementation,and the results show that this all-digital phase-locked loop has a wide frequency range,fast dynamic response,small steady-state error,which has certain application value.