基于差错概率传播模型的门级电路可靠度计算

Reliability Calculation for Gate-level Circuit Based on Error Probability Propagation Model

提出了一种差错概率传播模型,该方法首先将逻辑门的差错概率加载到连接导线上进行计算,再逐个计算逻辑门的正确输出概率,最后计算得到整个电路的可靠度.与传统概率转移矩阵方法比较,所提出的改进方法有效地减小了时间和空间复杂度,能适用于大规模电路的可靠性评估.

This paper builds a conductor error PTM propagation model, the logic gate of error PTM loading onto the wires are calculated, computed the correct logic gate output probability, finally a layer of door correct output probability is calculated, the probability is the reliability of the entire circuit. This method effectively reduces the time and space complexity, can apply to the reliability evaluation of VLSI circuit by comparing with traditional PTM.