基于FPGA的DDR3 SDRAM控制器设计与实现方法

Design and Implementation of a DDR3 SDRAM Controller Based on FPGA

DDR3 SDRAM作为新一代存储单元,在容量、速率和兼容性方面有很大提高,广泛应用在图像处理和高速数据采集系统中。本文通过研读DDR3 SDRAM的JEDEC标准,简要介绍DDR3 SDRAM的基本结构和工作原理,结合Xilinx公司提供的MIG软件开发环境,采用高传输速率、高可靠性、低成本、低功耗的Kintex-7系列FPGA实现DDR3 SDRAM控制器的设计~[1],通过Kintex-7开发套件进行联合仿真,性能达到预期设计目标,并在遥感图像压缩中有实际的应用。

As a new generation of memory cells, DDR3 SDRAM has been greatly improved in capacity, speed and compatibility and is widely used in image processing and high-speed data acquisition systems. In this paper, through the study of the JEDEC standard DDR3 SDRAM, briefly introduces the basic structure and working principle of DDR3 SDRAM, and combined with the MIG software development environment provided by Xilinx, using high transmission rate, high reliability, low cost, low power consumption Kintex-7 series FPGAs to implement the DDR3 SDRAM controller design-[1] and to perform co-simulation with the Kintex-7 Development Kit to achieve the desired design performance.