摘要
低密度奇偶校验码(LDPC)因其性能逼近Shannon限而被广泛应用于通信系统。为满足时变或有干扰的信道上可靠传输的通信要求,本文设计并实现了一种码长固定、码率灵活可变的LDPC码。利用近似下三角形式结构的校验矩阵直接编码,通过减少信息位和增加校验位,实现不同码率的灵活切换。译码基于简化和积译码算法得到的归一化最小和算法,并采用部分并行译码形式,在保证译码效率同时,兼顾FPGA资源消耗。硬件实现采用FPGA实现码长12960比特,码率2/3,1/3和1/6的LDPC码。
Low-Density Parity-Check Code （LDPC） is widely used in communication system for its near-Shannon limit performance. To satisfy the demand of communication in time variant channel or channel with interference, a multi-rate LDPC with fix code length is designed in this paper. Coding is based on a check matrix with approximate lower triangular structure directly, and multi-rate is achieved by decreasing information bits or increasing check bits. Decoding employs NMSA based on BP algorithm and partially-parallel architecture, thus decoding efficiency and FPGA source consume are both taken into consideration. Finally, a fix code length of 12960 bits LDPC with multi-rate of 2/3, 1/3 and 1/6 is implemented in FPGA.
出处
《现代导航》
2018年第1期41-46,共6页
Modern Navigation
关键词
LDPC
固定码长
多速率
FPGA
LDPC（Low-Density Parity-Check Codes）
Fix-Code-Length
Multi-Rate
FPGA
