P-flash串扰机制和解决方案的研究

The P-flash Disturb Mechanism and Solution Study

随着集成电路技术的快速发展,通过对作为将来低功耗和高速度读取的重要候选者的2T P-flash串扰结果的分析,从结构和功能方面出发找寻串扰产生的机制,进而在工艺和设计上提出相应的改善方法。通过在浅槽隔离下方注入合适的浓度,使以浅槽隔离区氧化硅为栅极氧化硅的选择晶体管可以承受更高的电压,从而改善编程单元造成的串扰。通过设计上的改进:(a)编程串扰:降低编程强度或是编程的时间,(b)擦除串扰:降低非选择区块的源端电压,(c)读操作串扰:降低读操作电压。通过改进的串扰措施,使P-flash的抗串扰能力增强,为2T P-flash作为低功耗,高速度的嵌入式闪存提供强有力的基础。

As the candidate of high speed and low power flash, P-flash still has the disadvantage to improve. By means of analyzing the influence of disturb on P-flash, we try to find out the mechanism behind the disturb base on structure and function attribute, and improve disturb in terms of process and design. For program disturb, we add the additional implant under the Shallow Trench Isolation to enhance the resistance of high voltage of transistor consisting of Select Transistor gate and STI oxide. The enhanced resistance of high voltage can improve the program disturb. And from the point of design, the program disturb can be improved via decreasing the program voltage and/or program pulse time; decreasing the drain voltage of un-selected sector to improve the erase disturb; and decreasing the read voltage to weaken the read disturb. All these improvements can boost the resistance of disturb for P-flash can strengthen the base of 2 T P-flash as the candidate for the embedded flash.