基于信号阻断的可配置低功耗乘法器设计

The Design of Reconfigurable Lower-Power Multiplier Based on Signal-Blocking

乘法器消耗的功率在整个电路中占有较大的比重,因此对其进行低功耗设计有着重要的意义。本文提出了基于信号阻断的可配置低功耗乘法器的设计。通过采用信号门控技术对配置乘法器进行划分,根据不同工作模式的模块构建电压岛,采用功率门控为模块提供电源电压,实现了一种可配置低功耗乘法器。仿真结果表明,在TSMC 65nm CMOS工艺下,所建议的乘法器电路在配置成低位乘法操作时,功耗和延时都有较大的优化。

Multiplier is the important arithmetic component. Its power consumption occupies significant ratio in the whole circuit. Hence,the low power deign is important for multipliers. In this paper,a reconfigurable low power multiplier which is based Signal blocking is designed. We use signal gating technology to divide the configuration multiplier,build the voltage island according to the different working modes,and use the power gating to provide the power supply voltage,implemented a configurable multiplier with low consumption. Under TSMC 65 nm CMOS process,the simulation results show that the power consumption and delay are optimized while the multiplier circuit is configured for low-bits multiplication.