一种新型低功耗D锁存器设计

A Novel Low Power D-Latch Design

本文提出了一种新型低功耗D锁存器,通过在直接交叉耦合D锁存器的接地端串联一个由输出反馈控制的NMOS管,部分消除了锁存器状态转换过程中的竞争现象,从而减小了电路的短路功耗,在数据保持阶段由晶体管的堆叠效应降低了电路的漏功耗。标准电源电压下HSPICE仿真测试结果表明,与直接交叉耦合D锁存器相比,新型D锁存器的漏功耗与动态功耗分别下降了13.5%和61.9%;与传输门D锁存器相比,漏功耗与动态功耗分别下降了9.3%和2.1%。应用新型D锁存器实现了4位伪随机序列信号发生器,仿真结果表明电路具有正确的逻辑功能,与传输门D锁存器构成的伪随机序列信号发生器相比动态功耗降低了18.9%,漏功耗降低了16.7%。

Regarding to the power consumption problem,a new low power D latch is proposed in this paper. A NMOS transistor is added between the cross-coupled inverters and ground and the transistor is controlled by the output. The new circuit eliminate the competition phenomenon of the previously proposed D latchand thus reducing the short power consumption. The proposed D latch and previous D latch are simulated using HSPICE with the BSIM4. 6. 4 predictive models at a 45 nm COMS process. According to the simulation results,the proposed D latch decrease 61. 9% in dynamic power and 13. 5% in leakage power compared to the cross-coupled D latch. Moreover,weapply the new D latch to pseudo random sequence signal generator and find it can functioncorrectly. The dynamic power and leakage power reduces 18. 9% and 16. 9%.