期刊文献+

多核与容错技术

原文传递
导出
摘要 随着多核处理器的流行,其高度的并行能力进一步提高了目前处理器的整体运行速度,同时,多核处理器本身的高集成度也使其故障率显著上升,从而限制了多核处理器在高可靠性方面的应用。本文描述了多核处理器上常用的容错技术和主要的研究成果,并分析和总结了目前处理器容错技术方面的研究热点和未来的发展方向。
作者 李文瑶
出处 《计算机与信息技术》 2009年第5期84-88,共5页 Computer & Information Technology
关键词 多核 CMP 容错 CRT CRTR
  • 相关文献

参考文献10

  • 1Linzhi Ning,Wenbin Yao,et al.Fault-Tolerant CMP Architecture Based on SMT Technology[].IEEE Micro Magazine.2007
  • 2Huiyang Zhou.A Case for Fault Tolerance and Performance Enhancement using Chip Multi-Processors[].IEEE Computer Architecture Letters.2006
  • 3Ricardo Fern′andez-Pascual,Jos′e M.Garc′a,et al.A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures[].IEEE HPCA.
  • 4Eric Rotenberg.AR-SMT:A Microarchitectural Approach to Fault Tolerance in Microprocessors[].Twenty-NinthAnnual International Symposium on.1999
  • 5Salloum C.E.,Steininger A.et al.Recovery mechanisms for dual core architectures[].thest IEEE international symposium on defect and fault tolerance in VLSI systems.2006
  • 6Sundaramoorthy K,Purser Z.et al.Slipstream processors:improving both performance and fault tolerance[].Proceedings of theth ACM international conference onarchitectural support for programming languages and operating systems.2000
  • 7Nickel J.B.,Somani A.K.REESE:A method of soft error detection in microprocessors[].Proceedings of the international conference on dependable systems and networks.2001
  • 8Gomaa,M.A.,Scarbrough,C.,Vijaykumar,T.N.,Pomeranz,I.Transient-Fault Recovery for Chip Multiprocessors[].IEEE Micro Magazine.2003
  • 9Mitra,S,Seifert,N,Zhang,M,Shi,Q,Kim,KS.Robust System Design with Built-In Soft Error Resilience[].IEEE Computer.2005
  • 10Reinhardt S K,Mukherjee S S.Transient Fault Detection via Simultaneous Multithreading[].Proceedings of the th Annual International Symposium on Computer Architecture.2000

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部