高性能主从模式动态可重构的SPI IP核设计

Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode

为满足系统芯片(SoC)中的串行外设接口(SPI)灵活配置的要求,设计了一种既可作为主机又可作为从机、支持4种数据传输模式、允许7种时钟传输速率的SPI IP核。该SPI IP核通过状态机来控制数据传输模块端口的方向,以此来解决主从模式下数据传输方向相反的问题,通过对移位寄存器的复用减少了逻辑资源消耗,利用时钟分频模块来实现不同传输速率下的数据交换,设计了配置数据传输模式的时钟极性和时钟相位等端口,方便了对SPI IP核的操作。结果表明:该SPI IP核符合SPI总线协议,在0.13μm工艺下消耗1 062个逻辑门,在系统工作频率80 MHz下的功耗约为0.395 7 mW。

To meet the flexible configuration requirements of serial peripheral interface（ SPI） in the System-on-a-Chip（ SoC）, the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine controls the port direction of data transmission module, which solves the problem of the opposite direction of data transmission in master and slave mode. The SPI IP core also multiplexes the shift register to reduce logic resource consumption. The clock frequency division module is designed to realize the data exchange with different transmission rates. In order to facilitate the operation of the SPI IP core, the ports including cpol and cpha that can configure the data transfer modes are designed. The results show that the SPI IP core is in good agreement with the SPI bus protocol. In addition,the circuit scale contains 1 062 logic gates under the 0. 13 μm technology and the power consumption is 0. 395 7 mW at a system operating frequency of 80 MHz.