基于高速CMOS时钟的数据恢复电路设计与仿真

Design and simulation of data recovery circuit based on high speed CMOS

文中基于2.5 GB/s的高速型数据收发器模型,采用SMIC 0.18μm的双半速率CMOS时钟进行数据的恢复处理。设计CMOS时钟主要包含:提供数据恢复所需等相位间隔参考时钟的1.25 GHz、16相频锁相环电路;采用电流逻辑模式前端电路构成的复用CDR环路;滤除亚稳态时钟的采样超前、滞后鉴相器;选择时钟与相位插值的控制时钟电路,以及基于折半、顺序查询算法的数字滤波电路。并对时钟进行数模混合仿真检测,测试结果表明:电路对于2.5 GB/s的差分输入数据,可快速高效完成数据恢复和时钟定时复位,具备极高的开发与应用前景。

In this paper, based on the 2.5 GB/s high speed data transceiver model, the SMIC 0.18 m dual half rate CMOS clock is used to recover the data. The design of a CMOS clock mainly includes： provide data needed to recover the phase of the reference clock interval 1.25 GHz, 16 phase frequency PLL circuit using current mode logic; a front-end circuit multiplexing CDR loop; sampling lead and lag phase detector filter metastable clock; clock circuit and clock phase control and interpolation. Based on the digital filter circuit, binary sequential query algorithm. And mixed simulation test on the clock, the test results show that the circuit for 2.5 GB/s differential input data can be completed fast and efficient data recovery and clock timing reset, with the development and application prospect of high.