RS码译码器的VLSI设计

VLSI DESIGN OF REED SOLOMON DECODERS

本文主要研究RS码译码器的VLSI设计优化方法。分析RS码译码算法的原理 ,将适合计算机仿真计算的算法转换成适合硬件实现的结构 ,并对其进行优化。设计并实现在FPGA上可以工作在 10MHz时钟频率下的单周期硬件译码器。

This paper focused on the VLSI design and optimal method of the Reed Solomon (RS) decoder. The first part of the paper includes the RS decoder working theory, and introduces how to convert the computer based algorithm to the hardware parallel architecture and its optimization. It finally demonstrates the performance of single period hardware RS decoder based on the FPGA which works at 10MHz clock.