摘要
基于25.2GHz整数电荷泵锁相环(CPPLL)的设计需求,采用TSMC90nm CMOS工艺设计了一款中心谐振频率为25.2GHz的低相位噪声LC压控振荡器.采用单平衡混频器的工作原理,重点分析并建立了关于尾电流源的相位噪声的数学模型,同时进行了合理优化.经过仿真及测试验证,压控振荡器的谐振频率范围为22.77~28.5GHz,相位噪声为-100dBc/Hz@1 MHz,电路功耗为15mA.
Based on the design requirement of the 25. 2 GHz integer charge pump phase-locked loop （CPPLL）, a low-phase noise LC voltage-controlled oscillator with a center resonant frequency of 25.2 GHz was designed by using the TSMC90 nm CMOS process. Based on the working principle of single-balanced mixer, the mathematical model of phase noise of tail current source was analyzed and established and reasonably optimized. The simulation and measure results indicated that the LC voltage-controlled oscillator had a resonant frequency range of 22. 75 - 28. 5 GHz, whose phase noise was -10O dBc / Hz @ 1 MHz, and the circuit power consumption wasl5 mA.
作者
武照博
王兴华
王征晨
WU Zhao-bo, WANG Xing-hua, WANG Zheng-chen(School of Information and Electronic, Beijing Institute of Technology, Beijing Silicon SoC Engineering Research Center, Beijing 100081, Chin)
出处
《微电子学与计算机》
CSCD
北大核心
2018年第4期63-67,共5页
Microelectronics & Computer
基金
国家自然科学基金项目(61301006)
关键词
LC压控振荡器
谐振频率
相位噪声
混频原理
LC voltage-controlled oscillator
resonant frequency
phase noise
frequency mixing theory
