一种基于FPGA的多通道复用鉴相器的设计与实现

Design and Implementation of a Multi-Channel Multiplexed Phase Detector Based on FPGA

针对导航接收机中多通道鉴相器资源占用较多与生产成本较高的问题,提出了一种基于FPGA的多通道复用鉴相器方案。该方案通过仲裁单元与FIFO缓存器对多通道相关结果进行仲裁与缓存,首先将多通道并行结果缓存排序为单通道串行结果,随后将FIFO中的串行结果输入到鉴相器中,最终使多通道复用同一鉴相器进行计算与处理。整个跟踪环路中的鉴相器个数由原来的每一通道配置一个变为多个通道复用一个,从而降低了资源占用与生产成本。

For the problem of more resource consumption and production costs of multi-channel phase detector in the navigation receiver,a multi-channel multiplexed phase detector based on FPGA is proposed. The multi-channel related results are arbitrated and cached by the arbitration unit and FIFO buffer. The multi-channel parallel data is transformed into single-channel serial data to send to FIFO,which send the serial data to the phase detector,and the same phase detector is used to calculate and process by multi-channel. The number of phase detector is decreased seriously to only one in the tracking loop,and resource consumption and production costs are saved correspondingly.