一种弹载数据链载波同步数字锁相环设计

Carrier Synchronizing Digital PLL Design for Missile-borne Data Link System

针对模拟锁相环稳定性差、参数调节困难的缺陷,利用双线性变换建立了模拟锁相环与数字锁相环设计参数的严格对应关系。采用现场可编程门阵列完成了基于软件定义无线电理念的全数字化Costas环设计及实现,在片内集成Microblaze软核以实现环路锁定频率及捕捉带性能的动态调整,环路收敛特性优异,经布局布线后静态时序工具报告最高工作频率可达466 MHz。设计通用性较强,可推广至各类软件无线电硬件平台开发。

To improve traditional analog PLL＇ s performance and stability, based on bilinear transformation, relationships between analog- domain and digital-domain design parameters were established strictly. A full-digitalized Costas loop was implemented on FPGA based on software defined radio technology, Microblaze soft core CPU was also instanced to modify loop lock frequency and capture band parameter dynamically. Convergence property was proved to be marvelous, and the maximum work frequency of routed design can attain 466 MHz. Presented design can be used for general SDR development because of highly-parameterized character.