一种用于前台校准的8位高线性度DAC

An 8 bit High Linearity DAC for Foreground Calibration

设计了一种用于12位折叠插值ADC前台校准的高线性度DAC。该DAC包括电流源、开关电路、译码电路和电流-电压转换器。电流-电压转换器采用带共模反馈和增益提高技术的运放,具有高的共模抑制比和高的输出线性度。电流源的版图设计中考虑了电流源匹配特性,提出了"V"型布局方案,有效抑制其梯度误差和对称误差,提高了DAC转换线性度。在TSMC 0.18μm CMOS工艺下对DAC进行仿真。结果表明,当输入信号频率为4.101 5 MHz、采样频率为25MHz时,DAC的有效位数达到7.97位。

A high linearity DAC for foreground calibration in a 12 bit folded-interpolation ADC was designed.The DAC included a current source,a switching circuit,a decoding circuit and a current-to-voltage converter.The current-to-voltage converter used an op-amp with common mode feedback and gain enhancement technique,which had achieved high common mode rejection ratio and high output linearity.In the layout design,the current source matching characteristics was considered,and a V-type current source layout scheme was proposed to effectively suppress the gradient errors and symmetry errors.The circuit was simulated in TSMC 0.18μm process.Simulation results showed that the DAC’s ENOB could reach 7.97 bit when the input signal frequency was 4.101 5 MHz and the sampling frequency was 25 MHz.