一种基于FPGA的卷积神经网络加速器的设计与实现

Design and Implementation of a FPGA-based Accelerator for Convolutional Neural Networks

本文提出了一种基于现场可编程门阵列(FPGA)的卷积神经网络(CNN)加速器的设计与实现方法,以期在资源和功耗受限的平台中为CNN的计算提供加速.首先,我们采用了数据量化的方式将网络参数从浮点数转化为定点数,从而降低了加速系统所需的硬件开销;其次,提出了一种从FPGA端发起数据访问的系统架构,避免了系统运行中因处理器对FPGA频繁干预而引起性能下降的问题;最后,为CNN的计算设计了高效的数据处理和缓存电路,从电路层面保证了加速器的计算效率.本文以交通标志识别(TSR)为应用场景将上述加速方案进行了板级实现.测试结果显示,识别时间为49ms,其中单个乘法器提供了0.081GOPS的性能,性能功耗比达到了6.81GOPS/W.与近年来相关领域文献对比,可以看出本文提出的方案在资源和功耗受限的情况下可以提供更高的性能.

In this paper,a convolutional neural network（CNN）acceleration method based on field programmable gate array（FPGA）is proposed,which aims to accelerate the calculation of CNN in resource and power limited platform.Firstly,we used the data quantization to convert parameters from the floating-point into fixed-point ones,which improves the hardware efficiency;Secondly,we proposed a system architecture that initiates data transaction from the FPGA side,which avoids the performance degradation caused by the processors frequent configuration.At last,we proposed an efficient processing element and data buffer for the CNN calculation,which improves the computational efficiency.In this paper,we implement all the method proposed above based on a CNN targeting at traffic sign recognition（TSR）.Test result shows that the hardware implementation introduces a 0.6%accuracy loss with 49 ms recognition delay,at which a single multiplier contributes 0.081 GOPS throughput and the performance power ratio reaches 6.81 GOPS/W.Compared with other works related in recent years,it can be seen that the proposed method can provide higher performance in the case of limited resources and power.