高性能多标准可配置Viterbi译码器设计与验证

Design and verification of high-performance multi-standard configurable Viterbi decoder

为了使Viterbi译码器广泛地应用于更多标准中,结合前向回溯译码和滑窗流水技术,同时ACS(Add-CompareSelect)部件通过减规约的操作减少异或延迟,提出一种高性能可配置Viterbi译码器。该译码器支持1 2,1 3,1 4码率,约束长度在5~9之间,生成多项式任意配置等参数,同时支持GPRS,Wi MAX,IS-95 CDMA,LTE,CDMA 2000等多标准。在对译码器进行设计的基础上,基于UVM验证方法学搭建一种模块级验证平台,完成Viterbi译码器模块级的功能验证,覆盖率达到99.4%。利用Synopsys Design Compiler工具进行综合,面积为0.2 mm2;在28 nm工艺,500 MHz主频下,功耗为38.3 m W,吞吐率为1.06 Gbit/s。结果表明,此译码器具有很好的灵活可配性,在移动终端有很好的应用前景。

To make the Viterbi decoder widely applied in more standards, a high-performance configurable Viterbi decoder is proposed by combining with pre-traeebaek （PTB） decoding and sliding-window pipeline technology, and reducing the XOR delay by means of the speeitleation subtraction operation in Add-Compare-Select （ACS） components. The decoder can support the code rates of 1/2, 1/3 and 1/4, constraint length of 5 to 9, polynomial generation arbitrary configuration and other parame- ters, and meanwhile can support multiple standards such as GPRS, WiMAX, IS-95 CDMA, LTE, and CDMA2000. On the ba- sis of the decoder design, a module-level veritleation plattBrm is established based on the UVM veritleation methodology to ac- complish module-level tunetional veritleation for the Viterbi decoder with the code coverage rate as high as 99.4%. The Synopsys Design Compiler tool is used to perf5rm integration, and the area is 0.2 mm2. In the 28 nm process with the main ti＇equeney of 500 MHz, the power consumption is 38.3 mW and the throughput rate is 1.06 Gbit/s. The results show that the decoder has good flexibility and compatibility, and has a good prospect in mobile terminal application.