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Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver 被引量:1

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver
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摘要 This paper presents the design and implementation of quadrature bandpass sigma–delta modulator.A pole movement method for transforming real sigma–delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma–delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 d B SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18μm CMOS technology,it achieves a total power current of 2.1 m A,and the chip area is 0.48 mm;. This paper presents the design and implementation of quadrature bandpass sigma–delta modulator.A pole movement method for transforming real sigma–delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma–delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 d B SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18μm CMOS technology,it achieves a total power current of 2.1 m A,and the chip area is 0.48 mm^2.
出处 《Journal of Semiconductors》 EI CAS CSCD 2018年第5期70-76,共7页 半导体学报(英文版)
基金 Project supported by the National Natural Science Foundation of China(Nos.61471245,U1201256) the Guangdong Province Foundation(No.2014B090901031) the Shenzhen Foundation(Nos.JCYJ20160308095019383,JSGG20150529160945187)
关键词 quadrature bandpass pole-movement sigma–delta image-rejection quadrature bandpass pole-movement sigma–delta image-rejection
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