数字通信系统中位同步时钟提取的改进设计

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

提出了一种提取位同步时钟的改进方法,通过在数字锁相环的鉴相器和控制器之间添加数字滤波器,减少了同步锁定后的抖动现象和随机噪声引起的相位抖动现象。使用FPGA芯片、采用VHDL硬件描述语言完成了系统设计,并在Quartus Ⅱ上进行仿真验证,结果表明,改进的系统可实现位同步时钟的准确提取,减少了相位抖动,提高了系统运行效率和抗干扰能力,保障了数字通信系统的同步性能。

An improved bit synchronization clock extraction method was proposed to reduce the phase jitter after synchronization and caused by random noise,by adding digital filter between phase detector and controller of digital phase locked loop. The design was completed by using FPGA chip and VHDL hardware description language,and performed the simulation verification on the Quartus Ⅱ. The results showed that the improved system can realize the accurate extraction of bit synchronization clock,reduce the phase jitter phenomenon,improve the system running efficiency and the ability of anti-interference,and guarantee the synchronization performance of the digital communication system.