应用于锁相环中的锁定检测电路设计

Design of Lock Detection Circuit for Phase-Locked Loop Applications

设计一种应用于锁相环(PLL)中的锁定检测电路(LDC).该电路采用移位寄存器的方式,当连续18个时钟周期内检测到锁定时,输出通过正反馈置为高电平.同时,在该电路中加入复位及强制锁定端口,采用SMIC 28nm CMOS标准工艺库实现.仿真结果表明:当电源电压为0.9V,参考频率在10~100 MHz范围内时,均可完成锁定检测.

A lock detection circuit（LDC）was developed for using in phase-locked loop（PLL）.A shift register was used in this circuit,and the output was at high level through positive feedback when the lock was detected during 18 consecutive clock cycles.Meanwhile,reset and force locking ports were added in the circuit.The circuit was designed in SMIC 28 nm CMOS process.The results of simulation showed that the lock detection could be completed when the supply voltage was 0.9 Vand the reference frequency was 10-100 MHz.