一种带RS触发器的预充电鉴相电路设计及分析

Research on The Design of Digital Phase Detector

结合“十五”国防重点预研课题“高性能RISC处理器核的研究”,文章提出一种带RS触发器的预充电鉴相电路设计,电路结构相对简单,抗干扰能力强,该鉴相器能够在犤-2π,2π犦范围内实现线性鉴频鉴相功能,在模拟环境下仿真结果表明其鉴相死区≤86ps,完全能够满足数字锁相环设计的要求。

Combined with the'tenth -five'national defense pre-research item'The Research of High Performance RIS C Processor Core',this paper gives a kind of phase dete ctor with RS flip -flop,which has a relatively simple structure and dood noise immunity performance.It also can re alize phase detected in the phase margin of.Under analog environment,the simulation result indicates that th e'dead zone'of this kind of phase detector is smaller than 86ps,this can meet the demand of the digital PLL.