摘要
为了提高准循环奇偶校验(QC-LDPC)码的译码速率,提出一种改进的部分并行QC-LDPC译码结构(IPPD)。根据QC-LDPC校验矩阵的特点,对子矩阵进行平均分层,采用部分并行译码结构加快译码迭代速度。实验仿真采用IEEE802.16e中码长为864、码率为0.5的QC-LDPC码进行验证。实验结果表明,当最大迭代次数为15、系统时钟频率为107 MHz时,该译码结构的吞吐率可达1Gbit/s。
In order to increase the speed of the quasi-cyclic low-density parity check code,An improved partially parallel decoder（IPPD）based on QC-LDPC is proposed.According to the characteristics of QC-LDPC check matrix,the sub matrix is divided into average layers,and the speed of iterative decoding is accelerated by using the partially parallel decoding structure.The experimental simulation is completed by using code length of 864 and code rate of 0.5 in IEEE802.16 estandard,the result shows that IPPD＇s throughput is 1 Gbit/s when the maximum number of iterations is 15 and the system clock frequency is 107 MHz.
作者
黄志成
陈紫强
谢跃雷
李亚云
HUANG Zhicheng;CHEN Ziqiang;XIE Yuelei;LI Yayun(Ministry of Education Key Laboratory of Cognitive Radio, Guilin University of Electronic Technology, Guilin 541004, China)
出处
《桂林电子科技大学学报》
2018年第2期92-96,共5页
Journal of Guilin University of Electronic Technology
基金
国家自然科学基金(61461015)
广西自然科学基金(2015GXNSFAA139302)
桂林电子科技大学研究生教育创新计划(2017YJCX24)
关键词
准循环奇偶校验
部分并行译码结构
子矩阵
quasi-cyclic Iow-density parity check
partially parallel decoder
sub matrix
