一种8位100 MS/s的低功耗流水线型ADC

An 8-bit 100 MS/s Low Power Pipelined ADC

基于0.35μm CMOS工艺,设计并制作了一种低功耗流水线型ADC。分析了ADC结构对功耗的影响,采用1.5位/级的流水线结构来最小化功耗,并提升速度。为进一步降低功耗,设计了一种不带补偿并可调节相位裕度的共源共栅跨导放大器(OTA)和改进的比较器。测试结果显示,该ADC在3V电源电压、100 MS/s采样速率下,功耗为65mW,面积为0.73mm2,在模拟输入频率为70.1 MHz和141 MHz下的无杂散动态范围(SFDR)分别为59.8dBc和56.5dBc。该ADC可应用于需要欠采样的通信系统中。

A low power pipelined analog-to-digital converter（ADC）was designed and implemented in a 0.35μm CMOS process.The effects of the ADC architecture on the power consumption were analyzed.A 1.5 bit/stage pipelined structure was adopted to minimize the power consumption and to improve the speed.To further reduce the power dissipation,a cascode operational transconductance amplifier（OTA）whose phase margin was adjustable without compensation had been implemented,and an improved low power comparator was also designed.The tested results showed that the ADC only dissipated 65 mW under 3 Vpower supply when sampled at 100 MS/s.The ADC delivered up to 59.8 dBc/56.5 dBc spur-free dynamic range（SFDR）with 70.1 MHz/141 MHz analog input tone respectively in under-sampling condition.The area of this ADC was 0.73 mm2.It could be used in many communication systems where under-sampling was required.