高速LVDS接口的FPGA设计与实现

Design and Implementation of High Speed LVDS Interface Based on FPGA

常规高速LVDS接口协议中,预置的同步序列会占用报文容量,且需在收端手工调整时钟数据对齐关系,降低了开发效率及平台间的兼容性。本文给出了一种基于8B/10B编码的,具有自动对齐功能的高速LVDS接口,并在Xilinx Virtex-7 FPGA平台上进行了接口测试,结果表明该接口可在600Mbps下稳定、可靠地传输数据。

In the conventional high speed LVDS interface protocol, the preset synchronization sequence will occupy the message capacity, and it is necessary to align the clock and the data manually at the receiving end, which will reduce the development efficiency and the compatibility between the platforms. In this paper, a high speed LVDS interface based on 8 B/10 B coding is presented, with which alignment can be accomplished automatically. The interface test on the Xilinx Virtex-7 FPGA platform shows that the interface can transmit data steadily and reliably under 600 Mbps.