基于Verilog HDL的并口总线设计与仿真

Design and Simulation of Parallel Bus Based on Verilog HDL

本文介绍了FPGA/CPLD作为外设挂接在MCU并口总线上的工作原理,使用Verilog HDL进行了模块化设计,并进行了仿真验证,还指出了使用双向端口(inout)和三态门(tri)应注意的问题,以期为相关学者提供参考。

This paper introduced the working principle of FPGA/CPLD as an external device mounted on MCU parallel port bus, modularized design with Verilog HDL, and carried out simulation verification. It also pointed out the problems that should be noticed when using two-way port （inout） and three state gate （tri）, in order to provide reference for relevant scholars.