基于FPGA的双线性对密码算法并行架构设计

A Parallel Architecture for Bilinear Pairings and Its Implementation Based on FPGA Platform

为提高双线性对加密算法在密码芯片中的执行速度,设计并实现了1种面向双线性对加密运算的并行硬件处理架构.该架构中运算单元由2个同步运行的算术核构成,实现了对双线性对算法中有限域运算的并行处理,提高了硬件资源的复用率.设计采用Verilog HDL编码,并基于FPGA实现.与传统方案相比,该方案在满足安全性的条件下实现了较快的速度和较小的面积,能够满足安全密码芯片的应用要求.

To achieve higher speed of pairing in cipher chips, a parallel dual processing engine architecture for pairing based cryptography was proposed. The processing unit consists of two arithmetic cores which run synchronously. The architecture achieved in parallel processing of pairing algorithms in finite field with high level of hardware reuse. The design was implemented by Verilog HDL and prototyped on FPGA platform with required security level. Compared with traditional works, the proposed design succeeded in pairing computation with higher speed and lower area cost, which suits industry application requirements of cipher chips.