一种用于光电标签的高电源抑制比的低功耗无片外电容低压差线性稳压器

A Low-power and High PSR Capacitor-less LDO Regulator Used for OEID

介绍了1种无片外输出电容结构的低压差线性稳压器(LDO).该结构采用TSMC 0.18μm标准CMOS工艺设计,利用体调制效应,提高了LDO的稳定性和其瞬态响应.电路的面积为300×165 μm^2,基于Cadence仿真,其最大负载电流为10 mA,输入电压2 V,输出电压为1.8 V.当负载电流为1 m A时,静态电流和电源抑制比分别为83.8μA和-82.6 d B.

An output capacitor-less low-dropout（LDO） regulator with a bulk-modulation is introduced.A proof-of-concept prototype is designed in TSMC 0.18 μm CMOS, to illustrate the enhancement that can be achieved by applying this technique. This circuit occupies only an active area of 300×165 μm2, and is simulated with Cadence. The proposed LDO regulator is able to deliver a load current up to 10 m A while regulating the output voltage at 1.8 V from 2 V supply voltage. While supplying 1 m A load current, quiescent current and power supply rejection（PSR） performance of proposed regulators are 83.8 μA and-82.6 d B, respectively.