基于泰勒展开的低成本e指数函数电路设计

Design and optimization of exponential function based on Taylor expansion

针对e指数函数运算中常见硬件实现方法资源消耗大的问题,提出基于泰勒展开的指数函数的优化实现。首先,通过对输入值进行区间压缩以减小泰勒展开计算的求解误差;其次,对e指数函数泰勒展开公式的系数进行修正;最后,在硬件实现中通过合并化简运算实现资源的精简。实验表明。该方法在TSMC 65 nm工艺下的面积为11 068μm^2,折合1 976门,运算结果的相对误差仅有10^(-2)~10^(-3)。相比于通常泰勒展开式法,关键电路少了3个加法器和3个乘法器,节省了60%的硬件资源,具有硬件资源消耗少、输入值范围宽、性能面积比高等优点。

Facing with the high resource consumption of common-used hardware implementation method for exponential function,this paper proposed a Taylor expansion-based implementation and optimization method. Firstly,it used range compression method to reduce the calculation error. Secondly,it corrected the coefficients of Taylor expansion formula. Thirdly,merge and simplify operations in hardware design realized the resource reduction. Experimental result shows that the circuit is11 068 μm^2 and 1 976 gates in TSMC 65 nm process,and achieves a relative error as low as 10^-2- 10^-3. Compared with common-used Taylor expansion implementation method,the proposed method reduces 3 adders and 3 multipliers,and saves about 60% hardware resources. The proposed method has the advantages of less hardware resource consumption,wide range input value and high performance area ratio.