极化码半平行SCL译码器的FPGA实现

Implementation of Semi-parallel SCL Decoding Algorithm Based on FPGA

在5G通信技术高标准要求下,极化码的出现给了研究人员新的方向。其在离散无记忆信道下,理论上能达到香农极限。目前,连续删除列表(Successive Cancellation List,SCL)译码算法公认具有较好的性能,然而平行结构的译码复杂度太高,而且计算单元利用率较低。为了取得硬件译码复杂度和译码性能的平衡,设计了基于半平行结构的极化码译码器,降低了对硬件资源的消耗,提高了计算单元的利用率。设计码长为1 024,码率为1/2,列表宽度L=32的极化码SCL译码算法。译码器在100 MHz的工作频率下的吞吐率可达到25.60 Mbps。

With the development of 5 G communication technology,a new channel coding algorithm is required to fulfill the higher requirement of 5 G.The emergence of polar code gives researchers a brand new direction.Nowadays,Successive Cancellation List（ SCL）decoding algorithm is widely regarded as the algorithm that can achieve good performance. However,the parallel SCL decoder is too complex,and its utilization ratio of process element is low.In order to achieve the balance between the complexity of hardware decoding and the decoding performance,a semi-parallel SCL decoder based on FPGA is designed.In the design,the block length N = 1 024 bits,the code rate is 1/2 and the list size L = 32.When the clock frequency is 100 MHz,the decoding throughput can be up to 25.60 Mbps.