一款12 Bit 1 GS/s射频采样的流水线模数转换器设计

A 12 Bit 1 GS/s RF Sampling Pipelined ADC

文章基于40 nm CMOS工艺设计一款12 Bit 1 GS/s射频采样的无采样保持放大电路的流水线ADC。首级采用了开关电容比较器结构提高了无采样保持放大电路带来的输入到Sub-ADC和MDAC采样通路的匹配度。后级Sub-ADC中采用对参考电压的预采样技术,缓解了后级比较器的压力。另外,首级处理3.5位量化精度,且理想级间增益为4,进一步缓解了首级MDAC对运放线性度、增益误差、输出信号电压摆幅的要求。采用高带宽高线性度的运放结构简化了模拟设计以及数字校准的复杂度。采样频率1 GHz,输入信号频率455 MHz,差分满摆幅1.2 V的情况下,经校准后ADC有效位数达到11.2位,信噪比70 d B,无杂散动态范围82 d B,总功耗约220 m W。

The paper presents a 12 bit 1 GS/s RF Sampling SHA-less Pipelined ADC, implemented on a 40 nm CMOS process. The proposed pipelined ADC employs switch capacitor voltage comparator（SC comparator）to handle the sampling networks mismatches at the input of the sub-ADC and the MDAC. Pre-charging reference voltagesrelaxesthe stress of comparatorsin backend sub-ADCs. To resolve 3.5 bit in its first stage and amplify the residue by factor of 4 relax the op-amp linearity, gain requirement, voltage swing in the first MDAC.Furthermore, using simple op-amp with high bandwidth and high linearity simplifies analog design and digital calibration. It achieves 11.2 bit ENOB, 70 d B SNR, 82 d B SFDR with a 455 MHz, 1.2 V full-scale input after calibration, while consuming 220 m W if digital calibration block is not considered.