用于视频传输的10G网络接口设计

Design of 10G Network Interface for Video Transmission

基于FPGA纯硬件电路的UDP/IP处理器设计,以实现高速处理为目的,对于现有的千兆以太网传输进行了提升,形成万兆以太网高速传输系统。主要对传输层、网络层、数据链路层做了深入研究。设计UDP/IP协议栈和万兆以太网数据链路层协议MAC控制器,由UDP/IP协议栈负责将视频数据在传输层和网络层进行封装解封装工作,由MAC控制器完成数据链路层的协议功能,视频数据通过摄像头经过视频解码芯片所产生。依照IEEE802.3-2005和IEEE802.3ae标准,使用ALTERA公司的Cyclone IV系列EP4CE6F17C8N对MAC控制器进行改进,解决以太网帧尾有效字节不定长问题。对CRC编码和校验设计两种方法进行比较,通过Quartus II和Model Sim仿真验证时序逻辑,各个模块运用硬件描述语言Verilog编写。

Based on the design of FPGA pure hardware circuit UDP/IP processor, aiming at realizing high-speed processing, the existing Gigabit Ethernet transmission has been upgraded to form a 10 G Ethernet high-speed transmission system. This paper mainly studies the transport layer, network layer and data link layer. A UDP/IP protocol stack and a 10 G Ethernet data link layer protocol MAC controller are designed. The UDP/IP protocol stack is responsible for the encapsulation and the MAC controller completes the protocol function of the data link layer, with the video data being generated by the camera through the video decoding chip. According to IEEE 802.3-2005 and IEEE 802.3 ae standards, the MAC controller is improved by using ALTERA Cyclone IV series EP4 CE6 F17 C8 N to solve the problem of indefinite length of effective bytes at the frames tail of Ethernet. The CRC coding and checking design methods are compared. The timing logic is verified by Quartus II and Model Sim simulations. Each module is written by hardware description language Verilog.