基于多级磁自旋存储器的Cache调度策略的设计

Design of Cache Scheduling Policies Based on MLC STT-RAM

多级磁自旋存储器(Multi-Level Cell Spin-Transfer Torque RAM,MLC STT-RAM)可在一个存储单元中存储多个比特位,有望取代SRAM用于构建大容量低功耗的最后一级Cache(Last Level Cache,LLC)。MLC STT-RAM的静态功耗在理论上为0,且拥有高密度和优秀的读操作特性,但它的缺陷在于低效的写操作。针对这一问题,在MLC STT-RAM Cache hard/soft逻辑分区结构的基础上,实现了MLC STT-RAM LLC写操作密集度预测技术以及相应Cache结构的设计。通过动态预测写操作密集度较高的Cache块,帮助MLC STT-RAM LLC减少执行写操作的代价。预测的基本思想是利用访存指令地址与相应Cache块行为特征的联系,根据预测结果决定数据在LLC中的放置位置。实验结果显示,在MLC STT-RAM LLC中应用写操作密集度预测技术,使得写操作动态功耗降低6.3%的同时,系统性能有所提升。

Multi-level cell（MLC）STT-RAM which can store multiple bits per cell,has been considered as a promising alternative to SRAM for the last-level Cache.MLC STT-RAM can reduce static power consumption significantly and has smaller cell size facilitates and better read performance.However,a major shortcoming of MLC STT-RAM Cache is its inefficient write operations.Based on hard/soft partition structure,this paper implemented write intensity prediction for energy-efficient MLC STT-RAM LLC.The objective of this architecture is to dynamically predict whether blocks will be written more than certain times thereby helping to reduce write latency and energy of MLC STT-RAM Cache.The key idea to solve this problem is to correlate write intensity with memory access instruction addresses.On top of that,this paper designed MLC STT-RAM LLC based on this predictor,in which prediction results are used to determine Cache line placement.Experimental results showed that this architecture reduces 6.3% of write energy consumption and improves system performance by 1.9% on average compared to the previous approach.