一种高速低噪声的发散型时钟树结构

A High-speed Low-noise Divergent Clock Tree

针对芯片级(TOP level)后端设计面积大、绕线资源少、时钟绕线长、时钟网络噪声大等特点,提出了一种针对芯片级设计中模块与触发器共存的高速低噪声发散性时钟树结构,并总结了一种实现该时钟树的方法。在同一芯片级设计中,采用该方法实现的时钟树结构与传统二叉树型时钟树结构进行比较,结果显示高速发散型时钟树比二叉树时钟树减少了26%的时钟延时、22%的时钟偏差和59%的串扰噪声,从而大大减少了时序违例的数目。

Aiming at the characteristics of full-chip level （TOP level） in back-end design, such as huge area, lack of routing source, long clock route and large clock network noise, a high-speed low-noise divergent clock tree structure is proposed for the co- existence of blocks and flip-flops in full-chip level design, and a way to implement the clock tree is summarized. In the same de- sign, the proposed clock tree is compared with the traditional binary tree.The results show that the high-speed low-noise divergent clock tree has a 27 percent of reduction in clock latency, 22 percent of reduction in clock skew and 59 percent of reduction in clock noise compared with the binary tree , which greatly reduces the number of tinting violations.