基于FPGA的数字下变频的设计与实现

Realization of Digital Down Converter Based On FPGA

数字下变频是中频信号处理系统中常用的技术手段,可在保证信号不失真的情况下有效降低采集信号的速率,便于后级处理器执行FFT等信号处理算法。提出一种基于FPGA的数字下变频方法,使用FPGA实现数控振荡器,产生正交的正、余弦样本信号,将采样的数字信号做正交化处理;实现级联积分梳状滤波器,合理抽取采样信号,降低信号频率;最后通过半带滤波器和FIR低通滤波器对整个信道进行整形滤波。充分发挥FPGA硬件并行化处理的优势,实现复杂的信号处理算法的高效执行,测试结果表明该方法可行有效,能够满足实际使用要求。

Digital down conversion is the commonly used technique in intermediate-frequency signal processing system, to reduce the rate of acquisition signal. A digital down-conversion method based on FPGA is proposed, which realizes the numerical control oscillator by FPGA, generates orthogonal positive and cosine samples signals. The cascaded integral comb filter is realized to reduce the signal frequency. Finally, the whole channel is shaped by half-band filter and FIR low-pass filter. The advantages of parallel processing of FPGA are fully utilized to realize the efficient execution. The test results show that this method is feasible and effective.