摘要
在许多实时高速信号处理中,需要使用FPGA硬件对复杂数字信号处理进行硬件加速或者预处理,例如广泛应用的矩阵求逆,方差等算法中[1],这些算法的关键都在于乘累加操作(MAC),目前的MAC操作多采用分裂式乘加器,文章设计一种高速4级流水MAC,对任意32bit数据进行高速的流水运算,在TSMC13工艺下进行综合,worst case下运行频率可超过400MHz。
It is necessary to use FPGA to process the complicated signal in many high-speed signal processing, such as pre-process or hardware-accelerating. The most important in the arithmetic is multiplication and addition（MAC）. This paper designs a distributed MAC, which include 4 pipeline stages and can calculate at 400 MHz clock in TSMC13 worst case.
作者
周啸
代明清
Zhou Xiao;Dai Mingqing(Xi7 an Aeronautics Computing Technique Research Institute,Aviation Industry Corporation of China,Xi？ an Shaanxi 710068,China)
出处
《信息通信》
2018年第5期27-29,共3页
Information & Communications
基金
航空科学基金资助项目(No.2016ZC31003)
关键词
乘加器
流水线
压缩算法
高性能
MAC
Pipeline
Compression Algorithm
High-Performance
