基于网表级的RM电路面积优化

Area Optimization of RM Circuits Based on Netlist Level

固定极性RM(Fixed-Polarity Reed-Muller,FPRM)电路面积优化是集成电路优化设计中的重要部分。针对传统网表级优化耗费时间长、逻辑级优化准确度低等问题。本文提出了一种新的基于网表级RM电路优化方案,使用穷举算法或者改进型布谷鸟算法获取部分最优极性或近最优极性对应的电路表达式,再经过DC(Design Complier)综合选取最小的电路面积及其电路结构。MCNC Benchmark电路测试结果表明,利用所提方法减少了需要网表级综合的电路数目,同时优化后得到的电路面积比逻辑级优化节省12%。

The area optimization of FPRM（ Fixed-Polarity Reed-Muller） circuit plays essential roles in the design of integrated circuits. Aiming at a variety of defects containing the long time-consuming in traditional netlist level optimization and low accuracy in logic level optimization, this paper proposed a method of RM circuit optimization based on the netlist level. With improved cuckoo search algorithm and exhaustive search algorithm, the circuit expression which corresponds to partial optimum polarity and near-optimal polarity can be obtained. Then by synthesis of Design Compile, the smallest area is selected. Results of MCNC Benchmark circuit tests show that the number of circuits in netlist level synthesis is reduced in use of proposed method and the circuit area is optimized by 12% compared with ones in logic level optimization.