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三维系统级封装中垂直互联结构的设计 被引量:5

Design of a Vertical Interconnection Structure Used in 3D System-in-Package
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摘要 随着集成密度的提高,三维叠层系统级封装(SIP)成为高密度电路集成的重要解决方案。在三维叠层封装中,垂直互联结构会影响跨层传输的信号性能,对射频信号有重要影响。从S波段三维集成SIP发展的需求出发,设计了一种应用于HTCC工艺的基板间垂直互联结构,并基于微波传输理论,利用电磁场仿真软件分析了不同互联结构的射频信号的传输性能。优化后的互联结构对S波段射频信号的插损小于0.2d B,驻波比低于1.1,具备良好的传输性能。该垂直互联结构具有工艺简单,成本低廉等优势,可以解决基板高密度垂直互联的问题,应用于射频微波电路的三维集成。 With the increase of integration density, 3D stacked system-in-package(SIP) has becomean important solution for high density circuit integration. In a 3D stacked package, the verticalinterconnection structure will affect the signal performance of cross-layer transmission and has animportant influence on RF signals. According to the requirement of the development of S-band 3Dintegrated SIP, a vertical interconnection structure between substrates for HTCC process is designed.Based on the microwave transmission theory, the transmission performance of RF signals with differentinterconnection structures is analyzed by using electromagnetic field simulation software. The insert lossof the optimized interconnection structure to the S-band RF signal is less than 0.2dB and the standingwave ratio is less than 1.1, thus having good transmission performance. The vertical interconnectionstructure has the advantages of simple process, low cost and the like, can solve the problem of high-density vertical interconnection of substrates, and is applied to the 3D integration of RF and microwavecircuits.
作者 汪粲星 张浩 刘海涛 WANG Canxing;ZHANG Hao;LIU Haitao(The 14th Institute of China Electronics Technology Group Corporation,Nanjing 210039,China)
出处 《微处理机》 2018年第4期10-13,共4页 Microprocessors
关键词 三维集成 SIP封装 垂直互联 3D integration SIP Vertical interconnection.
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