FPGA内嵌数字可编程延迟锁定环设计技术研究

Research on Design Technology of FPGA Enbedded Digital Programmable Delay Locking Ring

全数字控制实现的延迟锁定环DLL(Delay Locked-loop)电路,具有易于工艺集成、电路实现简单、无累积相位差、对温度和电源噪声不敏感等优点。基于SRAM配置,设计并实现可编程的内嵌于FPGA的DLL。通过剖析电路结构,对延迟单元、移相器、鉴相器、可编程控制器、输出占空比调整等单元模块进行分析和设计,使电路具有可编程移相、分频和倍频等功能。在0.22μm CMOS工艺模型下,工作频率可达300MHz。所设计的DLL是一款多功能可编程通用DLL,其功能涵盖了DLL的所有应用模式,适于嵌入FPGA芯片中,通过对其编程,可满足不同的FPGA用户对DLL的不同功能需求。

The delay locked loop （DLL） circuit realized by full digital control has the advantages ofeasy process integration, simple circuit implementation, no accumulated phase difference, andinsensitivity to temperature and power supply noise. Based on SRAM configuration, a programmable DLLembedded in FPGA is designed and implemented. By analyzing the circuit structure, the delay unit,phase shifter, phase detector, programmable controller, output duty ratio adjustment and other unitmodules are analyzed and designed so that the circuit has programmable phase shift, frequency divisionand frequency multiplication functions. Under the 0.22滋m CMOS process model, the operating frequencycan reach 300 MHz. The DLL designed is a multifunctional programmable universal DLL. Its functioncovers all application modes of the DLL and is suitable for embedding in FPGA chips. Beingprogrammed, it can meet the different functional requirements of different FPGA users for the DLL.