支持多从机全双工通信的IP核互联模型

Multi-Slave Interconnected Model for Supporting Full-Duplex Communication

针对CPU、SPI与UART之间数据传输效率低和CPU指令执行效率低的问题,提出一种支持数据并行处理的IP核互联模型。通过设计AXI4主机转接口和扩展3条ARMv4自定义指令实现CPU与AXI4总线的互联;并设计AXI4从机转接口,克服APB转换桥的不足,使AXI4总线可与多个从机同时进行支持流水线操作的全双工通信。整个设计采用Verilog进行结构级描述并通过了Modelsim仿真。实验结果表明,本文设计的模型与目前市面上的AXI4互联模型相比,具有很高的带宽和数据传输效率;CPU执行所有测试指令只需要36个时钟周期,在数据传输完毕之前有156个空闲时钟周期,从而具有很高的指令执行效率。

In order to solve the problems of low data transmission efficiency among CPU,SPI and UART,and the low CPU instruction execution efficiency,an IP cores interconnection model with the capability of processing parallel data is proposed. This model is realized by designing the AXI4 host converter interface and extending three ARMv4 custom instructions. By designing the AXI4 slave converter interface,the deficiency of the APB conversion bridge is overcome,and the AXI4 bus can run full duplex communications with multiple slave machines at the same time. Verilog is used in the whole design for structural-level description and Modelsim simulation is passed. The results show that the model designed in this paper has high bandwidth and data transmission efficiency compared with the current AXI4 interconnect model in the market and CPU has high instruction execution efficiency. It only needs 36 clock cycles to execute all the test instructions and has 156 idle clock cycles before the system completes data transmission.