期刊文献+

一种用于片上静电防护的新型闩锁免疫可控硅

A Novel Latchup-Immune SCR for On-Chip ESD Protection
下载PDF
导出
摘要 可控硅(SCR)被广泛应用于片上静电放电(ESD)防护。由于SCR的低维持电压特性,闩锁问题一直是其应用于高压工艺ESD防护的主要问题。改进设计了一种新型SCR器件,即MOS High-holding Voltage SCR(MHVSCR)。通过对SCR寄生三极管正反馈进行抑制,并提高维持电压,实现了闩锁免疫。详细分析了MHVSCR提高SCR维持电压的可行性、工作原理以及实现步骤。基于Sentaurus TCAD的仿真结果表明:设计的器件将传统器件的SCR维持电压从2.8V提高至15.88V,有效实现了SCR在12V工艺下的闩锁免疫能力。 Silicon controlled rectifier(SCR)is widely used in on-chip electro-static discharge(ESD)protection.However,due to the characteristic of low holding voltage of SCR,latchup is a major issue of SCR for ESD in high voltage process.An improved novel device named MOS high-holding voltage SCR(MHVSCR)was proposed.Latchup immunity was achieved by inhibiting the positive feedback of the parasitic transistor of SCR with increased holding voltage.Concurrently,the feasibility of increasing the SCR’s holding voltage in MHVSCR,the working principle and the implementing procedures were presented.Based on Sentaurus TCAD tools,the simulation results showed that the proposed device’s SCR holding voltage was increased from the traditional 2.8 V to 15.88 V.Therefore,the latchup immunity was implemented effectively in the 12 V process.
作者 仝壮 李浩亮 刘志伟 刘俊杰 尹沙楠 TONG Zhuang;LI Haoliang;LIU Zhiwei;LIU Junjie;YIN Shanan(School of Information Engineering,Zhengzhou Univ.,Zhengzhou 450000,P.R.China;School of Microelec.and Solid-State Electronics,University of Electronic Science and Technology of China,Chengdu 610000,P.R.China)
出处 《微电子学》 CAS CSCD 北大核心 2018年第4期524-528,共5页 Microelectronics
基金 深圳科学技术基金资助项目(SGJL20150217094454668)
关键词 静电放电 闩锁 可控硅 器件仿真 ESD latchup SCR device simulation
  • 相关文献

参考文献1

二级参考文献12

  • 1BART K, MERGENS M P J, TRINH C S, et al. ESD protection solutions for high voltage technologies[J]. Microelectronics Reliability, 2006, 46:677-688.
  • 2TAZZOLI A, MARINO F A, CORDONI M, et al. Holding voltage investigation of advanced SCR-based protection structures for CMOS technology[J]. Microelectronics Reliability, 2007, 47:1444-1449.
  • 3YANG Liu, WANG Yang, ZHOU Acheng, et al. Design, fabrication and test of novel LDMOS-SCR for improving holding voltage[J]. Solid-State Electronics, 2015, 103:122- 126.
  • 4SALCEDO A, LIOU J, LIU Zhi-wei, et al. Vinson TCAD methodology for design of SCR devices for electrostatic discharge (ESD) applications[J]. IEEE Transactions on Electron Devices, 2007, 54(4): 822-832.
  • 5GUIDO N, FRED K, JAN M L. Using an SCR as ESD protection without latch-up danger[J]. Microelectronics Reliability, 1997, 37(10/11): 1457-1460.
  • 6CHANG W J, KER M D. The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology[J]. IEEE Trans Device Mater Reliability, 2007, 7(2): 324-332.
  • 7VASHCHENKO V A, CONCANNON A, TER BEEK, et al. High holding voltage cascaded LVTSCR structures for 5.5 V tolerant ESD protection clamps[J]. IEEE Trans Device Mater Reliab, 2004, 4(2): 273-280.
  • 8MENEGHESSO Q TAZZOLI A, MAR1NO F A, et al. Development of a new high holding voltage SCR-based ESD protection stmcture[C]//IEEE International Reliability Physics Symposium. Phoenix, AZ, USA: IEEE, 2008.
  • 9LI Wang, RUI Ma, CHEN Zhang, et al. Sealable behavior modeling for SCR based ESD protection structures for circuit simulation[C]//IEEE International Symposium on Circuits and Systems (ISCAS). Melbourne, Australia: IEEE, 2014.
  • 10蒋苓利,张波,樊航,乔明,李肇基.ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR[J].Journal of Semiconductors,2011,32(9):34-37. 被引量:3

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部