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一种支持源代码级调试的全芯片仿真技术 被引量:1

A Whole Chip Simulation Technology for Debugging at Source Code Level
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摘要 源代码级调试对于嵌入式软件开发效率来说至关重要。传统的IC数字前端仿真平台在运行目标代码时,由于目标机是用硬件描述语言Verilog HDL描述的,因此无法进行源代码级调试,只能通过指令级调试或者查看输出波形来分析问题,然后再反向追溯源代码,开发效率低下。提出一种基于VPI技术的全芯片混合仿真方法,利用该方法可以实现目标机软件内核模型与片上复杂硬件外设模型相结合的混合仿真。由于使用了大量的硬件模型,因此该平台是功能完备的,又由于目标机是由软件实现的,因此该混合仿真平台可支持目标软件的源代码级调试。最后在一款工业级DSP的实际设计流程中的成功应用证明了提出方法的有效性。 It is very important for the embedded software developing effectiveness that debugging at the source code level.When running the target code on the traditional IC front-end simulation platform,it is impossible to debug at source code level because the target machine is described by hardware description language like Verilog HDL.The only way for debugging in this situation is to check out problems at the instruction level then to move backward to the source code.A whole chip hybrid simulation method based on VPI technology is proposed in this paper,through which,it is implemented that simulating the software kernel model and the complex hardware peripheral devices model together.The simulation platform is integrated because of using many hardware models and also is supporting debugging at source code level because its target machine model is implemented with software.Finally,a successful application in a practical industrial DSP design process has shown the effectiveness of the method proposed in this paper.
作者 王强 林广栋 耿锐 WANG Qiang, LIN Guangdong, GENG Rui(The 38th Research Institute of China Electronics Technology Group Corporation, Hefei 230088, China)
出处 《雷达科学与技术》 北大核心 2018年第3期281-285,共5页 Radar Science and Technology
基金 国家核高基重大专项(No.2012ZX01034001)
关键词 全芯片仿真 周期精确 软件调试 Verilog编程接口 whole chip simulation cycle accuracy software debugging Verilog procedural interface (VPI)
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