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一个基于日志结构的非易失性内存键值存储系统 被引量:5

A Log-Structured Key-Value Store Based on Non-Volatile Memory
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摘要 非易失性内存(non-volatile memory,NVM)技术是非常具有应用前景的计算机内存技术,将会对计算机存储层次结构产生极大的影响.NVM具有可字节寻址、可持久存储、低访问延迟等特点,这为DRAM和NVM在统一的主存储空间中的结合提供了巨大的机会.NVM可通过内存总线以及CPU相关指令进行数据访存,这使得在非易失性内存中设计快速的持久存储系统成为可能.现有的键值存储系统将NVM作为块设备使用,未能充分发挥NVM的性能.当硬件支持出现故障(例如高速缓存刷新)时,一些现有的键值存储系统无法保证数据的一致性.提出了一种基于日志结构的非易失性内存键值存储系统TinyKV,该系统利用键值数据负载的特性提出了一个静态并发、缓存友好的Hash表实现方案.TinyKV为每个工作线程维护单独的数据日志,以实现高并发性.此外,TinyKV采用日志结构技术进行内存管理,设计多层级内存分配器,以保证一致性.此外,系统通过减少对NVM的写入与缓存刷新指令,以降低写入延迟.实验显示:与传统的键值存储系统相比,TinyKV具有良好的吞吐性能与扩展能力. Non volatile memory (NVM) technologies are promising that would change the future of storage. NVM possesses many attractive capabilities such as byte addressability, low access latency, and persistence. It provides a great opportunity for the integration of DRAM and NVM in a unified main storage space. NVM could access data through the memory bus and CPU related instructions, which makes it possible to design a fast and persistent storage system in non volatile memory. Existing key value stores proposed for block devices implement NVM as block devices, which conceal the performance that NVM provides. A few existing key value stores for NVM fail to provide consistency when hardware supports (e. g. , cache flush) on power failures are unavailable. In this paper, we present a non volatile memory key value storage system, named TinyKV, which utilizes the log structure as its core framework. We propose a static concurrent, cache friendly Hash table implementation using the characteristics of the key value workloads. TinyKV separates the maintenance for data log of each worker thread in order to guarantee high concurrency. In addition, we implement the log structure technology for memory management and design a muhi tier memory allocator to ensure consistency. To reduce write latency, we reduce writes to NVM and cache flushing instructions by using cache flushing instructions. Our experiments demonstrate that TinyKV outperforms traditional key value stores in both throughput and scalability.
作者 游理通 王振杰 黄林鹏 You Litong;Wang Zhenjie;Huang Linpeng(Department of Computer Science and Engineering,Shanghai Jiao Tong University,Shanghai 20024)
出处 《计算机研究与发展》 EI CSCD 北大核心 2018年第9期2038-2049,共12页 Journal of Computer Research and Development
基金 国家重点研发计划项目(2018YFB1003302) 国家自然科学基金项目(61472241)~~
关键词 非易失性内存 日志结构 键值存储 HASH表 内存管理 non volatile memory (NVM) log structure key value store Hash table memory management
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  • 1Roberts I), Kgil T, Mudge T. Using non-volatile memory to save energy in servers[C] //Proc of the Conf on Design, Automation and Test in Europe. Belgium: European Design and Automation Association, 2009:743-748.
  • 2Qureshi M, Franceschini M, Lastras Montaflo L. Improving read performance of phase change memories via write cancellation and write pausing[C] //Proc of the 16th IEEE lnt Syrup on High Performance Computer Architecture. Piscataway, NJ: 1EEE, 2010:1 11.
  • 3Mishra A, Dong X, Sun G, et al. Architecting on chip interconnects for stacked 3D STT-RAM caches in CMPs [C] //Proc of the 38th lnt Syrup on Computer Architecture. New York: ACM, 2011:69-80.
  • 4Gun X, lpek E, Soyata T. Resistive computation: Avoiding the power wall with low-leakage, stt mram based computing [C] //Proc of the 37th Int Symp on Computer Architecture. New York: ACM, 2010:371 382.
  • 5Nigam A, Munira K, Ghosh A, et al. Model based study on energy and performance optimization for STT RAM [C/OL] //2011 Non-Volatile Memories Workshop. 2011. [2013 04 01]. http://nvmw, ucsd. edu/2011/.
  • 6Kong J, Zhou H. Improving privacy and lifetime of PCM based main memory [C] //Proc of the 40th Annual 1EEE/ IFIP Int Conf on Dependable Systems and Networks. Piscataway, NJ: IEEE, 2010:333-342.
  • 7Chhabra S, Solihin Y. i NVMM: A secure non volatile main memory system with incremental encryption [C] //Proc of the 38thlntSymponComputer Architecture. New York: ACM, 2011:177 188.
  • 8Sun (3, DongX, Xie Y, eta[. A novel architecture of the 3[) stacked MRAM L2 cache for CMPs [C] //Proc of the 15th IEEE Int Symp on High Performance Computer Architecture. Piscataway, N J: IEEE, 2009:239-249.
  • 9Kang H, Ryu K, Lee D, et al. Process variation tolerant all digital multiphase DLL for DDR3 interface [C] //Proc of IEEE Custom Integrated Circuits Conference. Piscataway, NJ: IEEE, 2010:1 4.
  • 10Zhou P, Zhao B, Yang J, et al. Energy reduction for STTRAM using early write termination [C] //Proe of IEEE/ ACM 2009 Int Conf on Computer Aided Design. Piseataway, NJ: IEEE, 2009:264-268.

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