可逆逻辑加法器电路实现

Reversible Logic Adder Circuit Implementation

本文从最少垃圾输出,少用常量输入,少用可逆门数来设计4位进位旁路加法器,并对设计中用到可逆逻辑门电路如Feynman门、TOF门、Fediken门和DPG门等进行电路设计,电路设计采用基于传输门和传输管逻辑等减少面积、降低功耗和提高性能,用SMIC 0.18 um工艺基于Virtuoso工具进行功能验证。

It is from the least garbage output,less constant input,less reversible gate numbers to design a 4 carry bypass adder,and the design of the use of reversible logic gate circuits such as Feynman,TOF,Fediken gate and DPG gate circuit. The circuit design is based on the transmission gate and the transmission tube logic to reduce the area and power consumption and improve the performance.At last,the circuit design uses SMIC0.18 um technology based on Virtuoso tools for functional verification.