期刊文献+

一种用于磁隔离驱动电路的编解码方案设计 被引量:2

Design of An Codec Scheme for Magnetic Isolation Drive Circuit
下载PDF
导出
摘要 采用体硅0.25μm BCD工艺,设计了一种用于磁隔离驱动电路的编解码方案,将需要传输的数字信号编码成两个不同宽度的高频脉冲,这些高频脉冲从变压器初级线圈耦合到次级线圈,并且由次级端电路检测,最后在输出端重新恢复成输入的信号.相对于传统的磁隔离驱动电路的编解码方案,本文设计的磁隔离驱动电路的编码和解码方式新颖,电路实现简单,使传输的信号延迟时间大大减小,并且工作频率更高.仿真结果表明,电路在3~5V的电压下能正常工作,可以实现最大数据隔离传输速率达到125 Mbps,延迟时间最大仅有8ns,静态电流1.64mA,动态功耗0.37mA/Mbps. Based on bulk silicon 0.25μm BCD process,a codec scheme for magnetic isolation drive circuit is designed.The digital signal to be transmitted is encoded into two high-frequency pulses with different widths.The primary winding of the transformer is coupled to the secondary winding and is detected by the secondary side circuit and finally restored to the input signal at the output.Compared with the codec scheme for traditional magnetic isolation drive circuit,the magnetic isolation drive circuit designed in this paper has a novel encoding and decoding method,and the circuit is simple to be realized.The delay time of the transmitted signal is greatly reduced and the frequency is higher.The simulation results show that the circuit can work normally under the voltage of 3-5 V,which can achieve the maximum data isolation transfer rate of 125 Mbps.The maximum delay time is only 8 ns,and the quiescent current is 1.64 mA with the dynamic power of 0.37 mA/Mbps.
作者 彭锐 蔡小五 刘海南 罗家俊 赵海涛 吴秀龙 PENG Rui;CAI Xiao-wu;LIU Hai-nan;LUO Jia-jun;ZHAO Hai-tao;WU Xiu-long(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 10029,China;Key Laboratory of Silicon Device Technology,Chinese Academy of Sciences,Beijing 100029,China;School of Electronics and Information Engineering,Anhui University,Hefei 230601,China)
出处 《微电子学与计算机》 CSCD 北大核心 2018年第9期42-46,共5页 Microelectronics & Computer
关键词 磁隔离 高频脉冲 还迟时间 功耗 magnetic isolation high-frequency pulse delay time power consumption
  • 相关文献

参考文献3

二级参考文献28

  • 1Razavi B,著.Design of Analog CMOS Integrated Circuits(影印本)[M].北京:清华大学出版社,2005.
  • 2Smith M J S. On the circuit analysis of the Schmitt trigger[J]. IEEEJournal of Solid-State Circuits, 1988, 23 (1): 292-294.
  • 3[美]贝克(Baker R J)等,著.CMOS电路设计、布局与仿真[M].陈忠建,译.北京:机械工业出版社,2006.
  • 4Wang Z H. CMOS Adjustable Schmitt Triggers [J]. IEEE Transactions on instrumentation and Measurement, 1991, 40 (3) : 601-605.
  • 5Filanovsky I M, Bakes H. CMOS Schmitt Trigger Design [J]. IEEE Transactions on Circuits and Systems, 1994, 41 (1):46-49.
  • 6Wang C S, Yuan S Y, Kuo S Y. Full-swing BICOMS Schmitt trigger[J].IEEE Proc.-Circuit Devices Syst, 1997, 144 (5): 303-308.
  • 7Hster A. Novel CMOS Schmitt Trigger with controllable Hysteresis [J].IEEE Electronics letters, 1992, 28 (7): 639-641.
  • 8Rongxiang Wu, Salahuddin Raju, Mansun Chan, et al. Wireless power link design using silicon-embedded inductors for brain-machine interface[C] // proceedings of the International Symposium on VLSI Design, Au- tomation, and Test (VLSI-DAT). Hsinchu: IEEE, 2012: 1-4.
  • 9Rongxiang Wu, Johnny K O Sin. A novel silicon-em- bedded coreless inductor for high-frequency power management applications [J]. IEEE Electron Device Letters, 2011(32) : 60-62.
  • 10Rongxiang Wu, Johnny K O Sin, Hui S Y. (Ron). Novel silicon-embedded coreless transformer for on- chip isolated signal transfer[J]. IEEE Magnetics Let- ters, 2011(2): 516-541.

共引文献5

同被引文献16

引证文献2

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部