摘要
智能剥离技术是制备绝缘体上锗(GeOI)衬底的常用方法。然而,由于锗与硅之间的热膨胀系数相差较大,硅锗键合界面较大的热应力可能导致键合对裂片或者解键合。通过对硅锗异质键合对的热应力问题进行理论分析,建立了硅锗双平板热应力模型。提出4种抑制热应力的实验方案,并得出优化退火条件是解决热应力问题最有效的办法。采用智能剥离技术在优化退火条件下成功制备了4英寸(1英寸=2.54 cm)晶圆级GeOI衬底,转移的锗薄膜厚度偏差小于2%,均方根表面粗糙度低至0.42 nm,喇曼光谱显示转移的锗薄膜内残余应力较小,制备的GeOI衬底可以为后续高迁移率器件制备或硅基Ⅲ-Ⅴ族异质集成提供材料平台。
The smart-cut technique is a common method for preparing germanium-on-insulator( GeOI) substrate. However,due to the large thermal expansion coefficient between germanium and silicon,the large thermal stress on the silicon-germanium bonding interface may result in the crack or debonding of the bonding pair. Based on the theoretical analysis of the thermal stress problems of silicongermanium heterogeneous bonding pairs,a silicon germanium bi-layer thermal stress model was established. Four experimental schemes for suppressing thermal stress were proposed,and it is concluded that the optimization of annealing conditions is the most effective way to solve the thermal stress problem. The4-inch( 1 inch = 2. 54 cm) wafer-scale GeOI substrate was successfully prepared by using smart-cut technique at optimized annealing conditions. The thickness deviation of the transferred germanium film is less than 2%,the root-mean-square surface roughness can be reduced to 0. 42 nm,and the Raman spectrum shows that the residual stress in the transferred germanium film is small. The prepared GeOI substrate can provide a material platform for subsequent high-mobility device fabrication or Si based Ⅲ-Ⅴheterogeneous integration.
作者
张润春
黄凯
林家杰
鄢有泉
伊艾伦
周民
游天桂
欧欣
Zhang Runchun;Huang Kai;Lin Jiajie;Yan Youquan;Yi Ailun;Zhou Min;You Tiangui;Ou Xin(State Key Laboratory of Functional Materials For Informatics,Shanghai Institute of Micro-System &Information Technology,Chinese Academy of Sciences,Shanghai 200050,China;University of Chinese Academy of Sciences,Beijing 100049,China)
出处
《半导体技术》
CAS
CSCD
北大核心
2018年第9期689-696,共8页
Semiconductor Technology
基金
上海市浦江人才计划资助项目(17PJ1410500)
关键词
绝缘体上锗(GeOI)
异质集成
智能剥离
晶圆键合
热应力
germanium-on-insulator ( GeOI )
heterogeneous integration
smart-cut
wafer bonding
thermal stress