基于FPGA消息识别和过滤的1553B总线监视器的设计

Design and Implementation of 1553B Bus Monitor Based on FPGA Message-Recognition and Filtering

在1553B总线应用中,总线消息的识别和过滤是总线监视器(BM)的扩展功能,在很多工程应用中具有非常重要的意义,尤其在高负荷实时通信中,总线上数据量庞大,给系统设计带来很大困难。在研究1553B总线协议的基础上,提取了消息分类的特征信息,设计了基于FPGA的具有信息识别和过滤功能的BM。该BM根据1553B总线消息特征进行消息识别,从而将总线上传输的信息处理成有意义的数据块;在此基础上,按照一定的策略进行消息过滤,仅保留过滤后的信息,从而降低总线负荷。采用VHDL语言、有限状态机技术和模块化设计,进行BM的开发,并通过仿真验证和硬件综合,测试结果表明本文设计的BM达到了设计目的。

In the application of 1553B bus, the extended function of the bus monitor （BM） is to identify- and filter the bus messages, which is very important in many engineering applications, especially in the high load of real-time communication on the bus, where the huge amount of data brings great difficulties to the system design. Based on the study of 1553B bus protocol, the feature information of message classification is extracted, and the BM with the functions of information identification and fihering is designed based on FPGA. The BM can identify- the messages according to the characteristics of 1553B bus messages, so that the information trans- mitted on the bus can be processed into meaningful data blocks. On this basis, the message filtering retains the filtered information with a specific strategy, consequently reduces the bus load. The VHDL language, finite state machine technology and modular design are used to develop and design BM. Through the simulation and hard- ware synthesis, the test results show that the design goal is achieved.